原文出处：http://www.fpga4fun.com/PCI-Express3.html

 

Packetized transactions

 

PCI express is a serial bus. Or is it? From the computer's perspective, it is a conventional bus where read and write transactions can be achieved.

 

The trick is that all operations are packetized. Let's assume the CPU wants to write some data to a device. It forwards the order to the PCI Express bridge which then creates a packet. The packet contains the address and data to be written and is forwarded serially to the targeted device, which de-packetizes the write order and executes it.

所有的操作都是基于数据包的，CPU想要往设备里写入数据，它先把命令发给PCI-E桥，由PCI-E桥创建数据包，包里面包含了地址和数据，然后串行发送到目标设备，由目标设备解包并执行命令。

 

What if the CPU wants to read? Same thing, the bridge forwards a packet to the targeted device, which now has to execute the read, create a return packet and send it to the bridge.

All that is pretty straighforward to do in practice thanks for the help from...

The PCI Express stack

Getting packets flowing reliably along the wires takes some magic. As packets are transmitted serially at very high speed, they have to be de-serialized/assembled, decoded at the destination (remove the 8b/10b encoding), de-interleaved (if multiple lanes are used), and checked against line corruption (CRC checks).

Sounds complicated? It probably is. The thing is, we don't really care because most of the complexity is handled in the "PCI Express stack", composed of three layers.

1. The physical layer.
2. The data link layer.
3. The transaction layer.

数据包是以非常高的速度进行串行传输的，所以需要一系列的解码，序列恢复和CRC校验。然而这么复杂的东西我们压根不用关心，有一个叫做"PCI Express stack"的东西来处理它们，这个stack包括了物理层、数据链路层和 事务层？(不知道怎么翻译，就叫它事务层吧)

The first two layers are the ones implemented for us in the PCI Express FPGA core (usually a combination of hard and soft core) and handling all the complexity. As a user, we work only in the transaction layer, where life is easy, the sky is blue and girls are beautiful.

前两层都交给FPGA core去实现了，作为用户，我们只需要关心事务层，这里生活如意，天空湛蓝，绿草如茵，美女遍地~(哈哈，看到这里笑出声)

In more details:

1. The physical layer: that's where the pins are toggling. The 8b/10b encoding/decoding and the lanes disassembly/reassembly are done there.
2. The data link layer: that's where data integrity is checked (CRCs) and packets are re-transmitted if required (hopefully a rare occurance).
3. The transaction layer: that's the user level. Once a packet arrives here, it is guaranteed to be good data.

Good data? That's great, that's what we want!

Let's see how working in the transaction layer looks like.

 

 

verilog-IT大道是有多无耻，我发一篇你立刻就转一篇，看看你们首页那乱的，文章也不分一下类，转载的也从来不标注出处。你那所有的文章都是从别人那里转来的吧，IT大道就是辣鸡！